Cypress Semiconductor /psoc63 /SRSS /RES_CAUSE

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Interpret as RES_CAUSE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RESET_WDT)RESET_WDT 0 (RESET_ACT_FAULT)RESET_ACT_FAULT 0 (RESET_DPSLP_FAULT)RESET_DPSLP_FAULT 0 (RESET_CSV_WCO_LOSS)RESET_CSV_WCO_LOSS 0 (RESET_SOFT)RESET_SOFT 0 (RESET_MCWDT0)RESET_MCWDT0 0 (RESET_MCWDT1)RESET_MCWDT1 0 (RESET_MCWDT2)RESET_MCWDT2 0 (RESET_MCWDT3)RESET_MCWDT3

Description

Reset Cause Observation Register

Fields

RESET_WDT

A basic WatchDog Timer (WDT) reset has occurred since last power cycle.

RESET_ACT_FAULT

Fault logging system requested a reset from its Active logic.

RESET_DPSLP_FAULT

Fault logging system requested a reset from its DeepSleep logic.

RESET_CSV_WCO_LOSS

Clock supervision logic requested a reset due to loss of a watch-crystal clock.

RESET_SOFT

A CPU requested a system reset through it’s SYSRESETREQ. This can be done via a debugger probe or in firmware.

RESET_MCWDT0

Multi-Counter Watchdog timer reset #0 has occurred since last power cycle.

RESET_MCWDT1

Multi-Counter Watchdog timer reset #1 has occurred since last power cycle.

RESET_MCWDT2

Multi-Counter Watchdog timer reset #2 has occurred since last power cycle.

RESET_MCWDT3

Multi-Counter Watchdog timer reset #3 has occurred since last power cycle.

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