Reset Cause Observation Register
RESET_WDT | A basic WatchDog Timer (WDT) reset has occurred since last power cycle. |
RESET_ACT_FAULT | Fault logging system requested a reset from its Active logic. |
RESET_DPSLP_FAULT | Fault logging system requested a reset from its DeepSleep logic. |
RESET_CSV_WCO_LOSS | Clock supervision logic requested a reset due to loss of a watch-crystal clock. |
RESET_SOFT | A CPU requested a system reset through it’s SYSRESETREQ. This can be done via a debugger probe or in firmware. |
RESET_MCWDT0 | Multi-Counter Watchdog timer reset #0 has occurred since last power cycle. |
RESET_MCWDT1 | Multi-Counter Watchdog timer reset #1 has occurred since last power cycle. |
RESET_MCWDT2 | Multi-Counter Watchdog timer reset #2 has occurred since last power cycle. |
RESET_MCWDT3 | Multi-Counter Watchdog timer reset #3 has occurred since last power cycle. |